A Novel VLSI Architecture for FDMA-MIMO Detector

Nowadays, the communication industry field is mainly focused on high data transfer and more channel capacity in mobile communication and to improve the spectrum efficiency, capacity of wireless network and reliability of the link. The area efficient architecture of 4×4 16-QAM Multiple Input Multiple Output (MIMO) detectors are mainly used for the wireless communication. An areaefficient symbol detector is proposed for MIMO communication systems with reduced buffer memory architecture. To design SC-FDMA MIMO received signal detector architecture using Euclidean distance technique. In this paper the internal MIMO detector get modified architecture and to improve the performance level. Proposed system is to increase throughput value, reduce the latency level and to reduce the power consumption level for channel allocation